Huawei’s Tau Scaling Law Targets 1.4nm Chips by 2031

Huawei Technologies Co. has unveiled a groundbreaking chip design architecture called the “Tau (τ) Scaling Law” (韬定律), marking the first time a Chinese company has proposed a new guiding principle for the global semiconductor industry. The company aims to achieve transistor density equivalent to 1.4-nanometer processes by 2031 through architectural innovation rather than relying on the most advanced chip manufacturing equipment to which it has been denied access.

A New Semiconductor Paradigm

On May 25, 2026, at the IEEE International Symposium on Circuits and Systems (ISCAS) in Shanghai, He Tingbo, Huawei Board Director and President of its Semiconductor Business Division, delivered a keynote titled “New Semiconductor Path in Practice” introducing the Tau Scaling Law. According to Caixin Global, the new theoretical framework shifts focus from traditional geometric scaling — shrinking transistor dimensions — to “time scaling,” which systematically reduces signal propagation delay (τ) across devices, circuits, chips, and systems.

The core technology enabling this shift is LogicFolding (逻辑折叠), a design methodology that stacks digital, analog, and memory circuits into vertical active layers. This approach breaks traditional planar layout boundaries, shortening critical-path wiring and reducing resistive and capacitive loads.

A Strategic Response to Export Controls

Since 2019, the United States has imposed escalating export controls restricting Huawei’s access to advanced semiconductor manufacturing tools, particularly extreme ultraviolet (EUV) lithography equipment, and chip design software. Huawei was also cut off from Taiwan Semiconductor Manufacturing Co.’s (TSMC) advanced foundry services.

The Tau Scaling Law is widely seen as a strategic response to these restrictions. Rather than attempting to match leading-edge process nodes directly, Huawei is innovating at the architecture and system level to achieve competitive performance using more accessible manufacturing processes. As CarNewsChina reported, by systematically compressing signal propagation delay, Huawei aims to drive performance and density gains without relying solely on the latest lithography equipment.

Proven Track Record and Ambitious Roadmap

Huawei has already designed and mass-produced 381 chips based on these principles over the past six years. The upcoming Kirin chip scheduled for Fall 2026 will be the first to fully adopt the LogicFolding architecture, with significant performance improvements:

• Transistor density increase: 53.5% (from approximately 130 million to 238 million transistors per square millimeter)
• Energy efficiency improvement: 41%
• Peak frequency increase: 12.7% (to 3.1 GHz)

Huawei’s roadmap projects Kirin CPU frequencies reaching 3.39 GHz by 2027, 3.71 GHz by 2028, and breaking the 4 GHz barrier by 2029. By 2031, the company expects its high-end chips to achieve transistor density equivalent to a 1.4 nm (14 Å) process — a target that places it on a competitive trajectory with industry leaders like TSMC, which plans to mass-produce 1.4-nanometer chips by 2028.

Industry and Market Reaction

The announcement triggered a surge in Chinese semiconductor stocks. Hua Hong Semiconductor hit its daily trading limit of +20%, while Semiconductor Manufacturing International Corp. (SMIC) surged 19%. The broader semiconductor index rose over 4%, reflecting strong market confidence in the new direction, as Caixin Global reported.

Yang Junping, a semiconductor analyst at QYResearch, told Chinese financial media Gelonghui that “the Tau Law captures the real contradiction in advanced chip evolution: the marginal returns from continued transistor shrinkage are declining, while interconnect, memory access, data movement, packaging I/O, and system communication are becoming the new performance bottlenecks.” He added that “the most noteworthy aspect is that China’s semiconductor industry is beginning to attempt to propose its own system-level evolution framework, rather than continuing to use others’ evaluation benchmarks.”

A Call for Global Collaboration

He Tingbo emphasized that Huawei’s approach is not intended to be proprietary. “We believe that openness and collaboration are key to driving ongoing progress in the semiconductor industry,” she stated. “No single company can independently find all the answers along the path of semiconductor evolution.” She invited global scientists and engineers to collaborate on the Tau Scaling Law, aiming for over 100 times hardware integration growth by 2035.

People’s Daily, in a commentary published on May 27, framed the breakthrough in broader strategic terms. As reported by People’s Daily, the state-affiliated newspaper wrote: “Technological autonomy is the lifeline — the tighter the external environment, the more firmly we must grasp the initiative of innovation.”

Analysis: A Complementary Path, Not a Replacement

Industry analysts caution that the Tau Scaling Law is not a direct replacement for Moore’s Law but rather a complementary path focused on system-level efficiency. Advanced process nodes still provide the most direct performance, power, and area (PPA) improvements. The 1.4 nm target refers to “equivalent transistor density” and system performance, not actual physical manufacturing at a 1.4 nm node — a technically significant distinction.

Furthermore, the Tau Law’s four-layer optimization system — spanning device, circuit, chip, and system levels — requires coordination across the entire semiconductor ecosystem, including foundries, EDA tool vendors, packaging suppliers, and software developers. While 381 chips have already been produced using these principles, the full LogicFolding architecture in the upcoming Kirin chip will be the first real test of the technology’s commercial viability.

What to Watch For

The coming months will be critical for Huawei’s semiconductor ambitions. The Fall 2026 Kirin chip launch will provide the first real-world benchmark of LogicFolding’s performance against competitors using advanced nodes. Meanwhile, the global semiconductor industry will be watching to see whether the Tau Scaling Law gains adoption beyond Huawei’s own products and how U.S. export control authorities may respond to this architectural workaround. He Tingbo’s academic paper, “A Time Scaling Theory for Multi-Layer Electronic Systems,” has been submitted to the Chinese Academy of Sciences preprint platform, opening the door for broader scientific scrutiny and validation.