IBM Unveils World’s First Sub-1nm Chip, Extends Moore’s Law

IBM has announced a landmark breakthrough in semiconductor technology, unveiling the world’s first sub-1 nanometer (nm) chip built on a revolutionary new 3D transistor architecture called “nanostack.” The 0.7 nm (7 angstrom) node chip packs nearly 100 billion transistors onto a fingernail-sized die—roughly double the density of IBM’s previous 2 nm chip unveiled in 2021—and promises up to 50% higher performance or 70% greater energy efficiency.

Announced ahead of the VLSI 2026 symposium, the innovation positions IBM at the forefront of semiconductor research and is projected to extend Moore’s Law for at least another decade, according to the company’s official press release.

A New Architecture for the Angstrom Era

To achieve this breakthrough, IBM researchers developed an entirely new transistor architecture called “nanostack”—the industry’s first known three-dimensional, nanosheet-based design. Unlike traditional approaches that shrink transistors across a flat plane, nanostack vertically stacks and staggers transistors in two layers using 3D sequential integration, effectively building upward rather than just shrinking sideways.

Each transistor in the demonstrated structure uses three nanosheets that are each roughly 15 atoms thick, spaced 9 nanometers apart. Two such devices are then bonded vertically using an ultra-thin dielectric process that IBM describes as a key innovation. Because the top and bottom transistors can use different channel materials, dielectrics, and metals, the architecture enables per-tier optimization of performance and power efficiency.

“With our new nanostack architecture, we’re not just making smaller transistors, we’re reinventing how chips are built to deliver dramatically more power and energy efficiency,” said Jay Gambetta, Director of IBM Research and IBM Fellow, in the IBM Research blog. “This industry-first innovation continues IBM’s legacy of leading in next-generation technologies and sets the foundation for the next era of computing.”

Transformative Performance Gains

IBM’s published technical results report that the new chip offers a substantial leap in capability. Compared to its 2 nm node chips, the nanostack architecture delivers up to 50% higher performance at the same power, or up to 70% greater energy efficiency. The company also highlighted a 40% improvement in SRAM cell area scaling—the biggest leap in at least a decade—which is particularly critical for AI workloads that depend on high-bandwidth on-chip memory.

“Absolutely, it’s transformational,” said Dan Hutcheson, Vice Chair of TechInsights, as reported by MIT Technology Review. “This puts another 10, 15 years on the roadmap.”

The implications for AI computing are particularly significant. IBM researchers estimate that AI accelerators built on 7 angstrom technology could deliver approximately 9,000 TOPS (trillions of operations per second)—roughly six times today’s capabilities. This could potentially cut large language model training time from approximately three months to just two weeks.

Huiming Bu, IBM Vice President of Global Semiconductor R&D, told ZDNet: “Everyone demands more performance, but no one wants to pay the bill for the power. This new innovation can improve performance by 50% compared to the best available chip today, and at the same time can reduce power by 70% if you choose to manage your power in that computing, which is a very critical component for AI.”

From Lab to Production

The research was conducted at IBM’s Albany, New York facility in partnership with ASML, Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions. The Albany lab is set to house a High Numerical Aperture Extreme Ultraviolet (High-NA EUV) lithography tool, essential for printing circuits at angstrom-scale dimensions.

IBM has experimentally validated the nanostack architecture with functional CMOS inverters demonstrating expected switching behavior, confirming the technology can be physically built and supports real computation. However, the sub-1 nm chip remains a research achievement for now. IBM sees a path to production within the next five years, with earliest adoption expected at the sub-1 nm node.

Industry Context and Competitive Landscape

IBM is primarily a research and IP licensing entity in semiconductors rather than a manufacturer. The technology will need to be transferred to manufacturing partners such as Rapidus, Samsung, Intel, or TSMC. Intel, Samsung, and TSMC are also developing complementary field-effect transistor (CFET) technologies, though IBM claims its staggered nanostack design offers unique advantages in wiring simplicity and performance.

Qing Cao, Professor of Materials Science and Engineering at the University of Illinois at Urbana-Champaign, told MIT Technology Review that IBM’s work is “transformative” because it demonstrates how to stack transistors on a full wafer using a state-of-the-art manufacturing line, while noting that manufacturing complexity and thermal management remain significant challenges.

What’s Next

IBM’s internal roadmap projects nanostack scaling through multiple generations: 7 angstrom (Å), 5 Å, 3 Å, and potentially down to 1 Å. The company expects the architecture to underpin CPUs, GPUs, mobile SoCs, and SRAM arrays, eventually replacing nanosheet as the mainstream leading-edge architecture starting at the sub-1 nm node.

With the generative AI boom driving enormous demand for computing power, chips that offer 70% better energy efficiency directly address the power consumption crisis in AI data centers. As IBM’s Forbes coverage noted, the promised efficiency gain matters because the generative-AI boom has turned chip power consumption into one of the computing industry’s biggest problems.

For an industry that has long debated the end of Moore’s Law, IBM’s nanostack breakthrough offers a clear answer: the roadmap extends well into the next decade, and the Angstrom era has officially begun.